Analysis of threshold voltage instabilities in semi-vertical GaN-on-Si FETs

We present a first study of threshold voltage instabilities of semi-vertical GaN-on-Si trench-MOSFETs, based on double pulsed, threshold voltage transient, and UV-assisted C-V analysis. Under positive gate stress, small negative V-th shifts (low stress) and a positive V-th shifts (high stress) are observed, ascribed to trapping within the insulator and at the metal/insulator interface. Trapping effects are eliminated through exposure to UV light; wavelength-dependent analysis extracts the threshold de-trapping energy approximate to 2.95 eV. UV-assisted CV measurements describe the distribution of states at the GaN/Al2O3 interface. The described methodology provides an understanding and assessment of trapping mechanisms in vertical GaN transistors. (C) 2020 The Japan Society of Applied Physics