Article
Engineering, Electrical & Electronic
Ivan Padilla-Cantoya, Jesus E. Molinar-Solis, Agustin S. Medina-Vazquez, Marco A. Gurrola-Navarro, Luis Rizo-Dominguez, Eric F. Gutierrez-Frias
Summary: The class AB two stage op-amp presented features accurate static current control, symmetric signal paths to the output transistors, and is suitable for environments with uncertain or variable supply voltages. The implementation of a conceptual floating voltage source in the output stage allows adoption of positive and negative values indistinctively. This design requires few additional devices and power consumption compared to conventional schemes, and operates within a wide range of supply voltages.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
(2021)
Article
Computer Science, Information Systems
Leila Safari, Gianluca Barile, Vincenzo Stornelli, Shahram Minaei, Giuseppe Ferri
Summary: This paper presents the implementation of a low-voltage class AB second generation voltage conveyor (VCII) with high current drive capability, featuring simple realization and good overall performance. Proper solutions and techniques were used to achieve high signal swing and high linearity at Y, X and Z ports of VCII as well as low-voltage operation. The operation of the proposed VCII was verified through SPICE simulations, showing good performance at different ports.
Article
Engineering, Electrical & Electronic
Behnam Abdoli, Seyed Javad Azhari
Summary: This paper presents a novel low-voltage low power fully differential class AB current output stage with high linearity and unique current drive capability. The proposed circuit minimises the channel length modulation effect to achieve high linearity and avoids cascade structure to perform well in low-voltage applications. The circuit's properties are verified through simulations and it demonstrates impressive performance metrics such as high output current, low THD, and low power consumption. This novel circuit outperforms other current output stages by a significant margin.
INTERNATIONAL JOURNAL OF ELECTRONICS
(2023)
Article
Engineering, Electrical & Electronic
Mohammad Barzgari, Ali Ghafari, Amir Nikpaik, Ali Medi
Summary: This article presents a high-performance even-harmonic class-E CMOS oscillator with excellent phase noise performance, achieved through a customized resonant circuit and ZVS/ZDS conditions to improve power efficiency and reduce noise-to-phase noise conversion. The implemented oscillator performs well at high frequencies and exhibits improved characteristics compared to existing CMOS oscillators.
IEEE JOURNAL OF SOLID-STATE CIRCUITS
(2022)
Article
Telecommunications
Caffey Jindal, Rishikesh Pandey
Summary: This paper presents a low output resistance and high slew rate FVF cell, which consists of cascoding transistors and bulk-driven transistors, offering advantages such as low output resistance, high current driving capability, and occupying less chip area.
WIRELESS PERSONAL COMMUNICATIONS
(2022)
Article
Chemistry, Analytical
Jose C. Garcia-Montesdeoca, Juan A. Montiel-Nelson, Javier Sosa
Summary: This work presents a transimpedance amplifier (TIA) based on a voltage conveyor structure, designed to achieve high gain, low noise, low distortion, and low power consumption. The voltage buffer is designed for low distortion and power consumption, while the regulated cascode is designed for low noise and high gain. The fabricated TIA exhibits excellent performance, including a high transimpedance gain and wide bandwidth, making it a promising solution for logic and mixed-mode designs.
Article
Engineering, Electrical & Electronic
Francesco Centurelli, Riccardo Della Sala, Pietro Monsurro, Pasquale Tommasino, Alessandro Trifiletti
Summary: This paper proposes a novel ultra-low-voltage AB class operational transconductance amplifier that utilizes local common mode feedback to enhance performance and robustness. Through extensive testing and comparison, it has been shown that the amplifier has good small-signal figures of merit and performs well in large-signal scenarios, even with worst-case slew rate.
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS
(2022)
Article
Engineering, Electrical & Electronic
Islam Mansour, Marwa Mansour, Mohamed Aboualalaa
Summary: This work presents two new structures of inductor to improve the performance of K-band class-C VCOs. By introducing defected ground structure, the problems of poor-quality factor and low self-resonance frequency of conventional inductors are solved. The proposed inductors have wideband characteristics and increased Q-factor, allowing for the design of high-performance VCOs.
MICROELECTRONICS JOURNAL
(2022)
Article
Engineering, Electrical & Electronic
Ali Azam, Zhidong Bai, Jeffrey S. Walling
Summary: This paper presents an ultra-low power, integrated pulse width modulated (PWM) temperature sensor, which generates temperature output by comparing temperature-dependent voltage with temperature-independent voltage. The sensor utilizes a feedback-corrected 2-transistor voltage reference cell to provide steady output across temperature, enabling operation with low supply voltages and minimal power consumption. The sensor allows for robust temperature measurement by utilizing a ratio of output pulse-widths.
IEEE SENSORS JOURNAL
(2021)
Article
Computer Science, Information Systems
Jorge Perez-Bailon, Belen Calvo, Nicolas Medrano
Summary: This paper presents the design and postlayout simulation results of a capacitor-less low dropout (LDO) regulator fully integrated in a low-cost standard 180 nm CMOS technology, which regulates the output voltage at 1.2 V from a 3.3 to 1.3 V battery over a -40 to 120 degrees C temperature range. Achieving ultralow power consumption and minimum area consumption, including a reference voltage V-ref = 0.4 V, the regulator uses a high-gain dynamically biased folded-based error amplifier topology optimized for low-voltage operation to enhance regulation-fast transient performance trade-off.
Article
Computer Science, Hardware & Architecture
Juan Jesus Ocampo-Hidalgo, Jesus Ezequiel Molinar-Solis, Noe Oliva-Moreno, Victor Hugo Ponce-Ponce, Marco A. Ramirez-Salinas
Summary: This article introduces a new CMOS voltage follower with improved performance compared to traditional followers. The proposed follower has lower output impedance and better behavior, as demonstrated through circuit simulations and fabrication of a test cell.
IEEE CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING
(2021)
Article
Computer Science, Information Systems
Andrea Ria, Alessandro Catania, Paolo Bruschi, Massimo Piotto
Summary: A voltage reference capable of working with supply voltages down to 0.5 V is presented in this work, which combines a classic CMOS bandgap core with low-threshold or zero-threshold MOSFETs. The proposed circuit is demonstrated to have advantages in theoretical analysis and numerical simulations, and experimental results show it generates a reference voltage of 220 mV with low temperature sensitivity and quiescent current consumption.
Article
Engineering, Electrical & Electronic
Nardi Utomo, Boon Chiat Terence Teo, Xian Yang Lim, Venkadasamy Navaneethan, Ziming Liu, Chong Boon Tan, Liter Siek
Summary: This paper presents a novel class H audio amplifier design that allows full class H operating region, optimizing the efficiency of the class H audio amplifier architecture. The proposed class H audio amplifier is designed and fabricated in GF 55nm BCDLite process, occupying 2.01mm(2) total chip area. It achieves the lowest A-weighted THD+N of -82dB and-81.5dB at 1kHz and 20kHz, respectively, and also achieves 85.1% peak power efficiency.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
(2023)
Article
Engineering, Electrical & Electronic
Tingxu Hu, Mo Huang, Yan Lu, Xiu Yin Zhang, Franco Maloberti, Rui Martins
Summary: This article presents a 2.4-GHz differential class-DE synchronous rectifier with near-optimum ZVS, ZCS, and impedance matching achieved through a differential topology. An adaptive bias circuit is used to adjust gate bias voltages with input power for ZVS/ZCS operation within a wide power range. The chip fabricated in a 65-nm CMOS process achieves peak power conversion efficiency of 68.5% at 9-dBm input power with 250-ohm load resistance, with a measured input power range of 16 dB when PCE > 40%.
IEEE TRANSACTIONS ON POWER ELECTRONICS
(2021)
Article
Engineering, Electrical & Electronic
Goncalo Almeida, Zhaochu Yang, Tao Dong, Paulo Mendes, Yumei Wen, Ping Li
Summary: This paper presents a current starved voltage-controlled oscillator (VCO) based on the standard 0.13-mu m CMOS process, incorporating a power management circuit (PMC) to generate an average periodic signal at 84.81 kHz. A voltage reference is implemented to ensure stable periodic signal output, utilizing subthreshold and deep triode MOSFETs. The proposed architecture achieves a linear sensitivity of 0.49%/V and a power consumption of 3.546 mu W at 3 V supply voltage, suitable for a time-control local oscillator in vibration energy harvesters.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2021)
Article
Mathematics, Applied
Ludovico Minati, Mattia Frasca, Gianluca Giustolisi, Pawel Oswiecimka, Stanislaw Drozdz, Leonardo Ricci
Editorial Material
Computer Science, Hardware & Architecture
Giulia Di Capua, Nuno Horta, Francisco V. Fernandez, Gunhan Dundar, Salvatore Pennisi, Gaetano Palumbo, Massimo Alioto, Gianluca Giustolisi
INTEGRATION-THE VLSI JOURNAL
(2018)
Article
Engineering, Electrical & Electronic
Crispino S. Abella, Salvo Bonina, Antonino Cucuccio, Salvatore D'Angelo, Gianluca Giustolisi, Alfio D. Grasso, Antonio Imbruglia, Giorgio S. Mauro, Giuseppe A. M. Nastasi, Gaetano Palumbo, Salvatore Pennisi, Gino Sorbello, Antonino Scuderi
IEEE SENSORS JOURNAL
(2019)
Article
Engineering, Electrical & Electronic
Gianluca Giustolisi, Gaetano Palumbo
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
(2019)
Article
Engineering, Electrical & Electronic
A. Ballo, A. D. Grasso, G. Giustolisi, G. Palumbo
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
(2019)
Article
Engineering, Electrical & Electronic
Gianluca Giustolisi, Gaetano Palumbo
Summary: This paper introduces a new procedure for designing a generic three-stage amplifier based on settling-time specifications. The procedure extends the analysis of settling-time from pure two- or three-pole amplifiers to a generic amplifier with one or two zeros, even in the right-half plane. The validity of the proposed approach is demonstrated through the design example of a three-stage CMOS amplifier suitable for switched-capacitor applications.
MICROELECTRONICS JOURNAL
(2021)
Article
Computer Science, Information Systems
Gianluca Giustolisi, Gaetano Palumbo
Summary: An analytical criterion has been established for optimizing the small-signal settling time in three-stage amplifiers based on equaling two exponential decays of the step response. By considering slew-rate effects, a useful design strategy for three-stage operational transconductance amplifier is provided. Extensive time-domain simulations on a transistor-level design in a 65-nm CMOS process have confirmed the validity of the proposed approach.
Article
Engineering, Electrical & Electronic
Gianluca Giustolisi, Gaetano Palumbo
Summary: This paper analyzes the design approach for three-stage CMOS operational transconductance amplifiers and proposes a design scheme suitable for settling-time specifications. A design example is presented to validate the proposed method.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
(2021)
Article
Computer Science, Information Systems
Gianluca Giustolisi, Paolo Finocchiaro, Alfio Pappalardo, Gaetano Palumbo
Summary: A new silicon photomultiplier model is proposed in this paper, utilizing the Verilog-a behavioral language for transistor-level circuit simulations. The model includes traditional electrical and statistical models to describe the device noise, along with a procedure for parameter extraction validated through comparison of simulations to experimental results.
Article
Computer Science, Information Systems
Francesco Centurelli, Gianluca Giustolisi, Salvatore Pennisi, Giuseppe Scotti
Summary: This paper presents an approach to design analog building blocks for nanometer systems on a chip (SoCs) using digital standard-cells, ensuring robustness against PVT variations. It introduces an Analog Body Bias Generator (ABBG) that utilizes bulk voltages to control the current and voltage of CMOS inverters. The design flow for the standard-cell based analog building blocks is also discussed, along with an example application of a low-power operational transconductance amplifier (OTA).
Proceedings Paper
Engineering, Electrical & Electronic
Gianluca Giustolisi, Gaetano Palumbo
Summary: The settling-time in single-pole OTAs is analyzed with consideration of slew-rate limitations, and a useful design equation is provided and extended to three-pole OTAs. The design procedure is validated through simulations.
2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
(2021)
Article
Engineering, Electrical & Electronic
Gianluca Giustolisi, Gaetano Palumbo
Summary: This paper proposes a new strategy for the design of ultra-low-power CMOS operational transconductance amplifiers (OTAs) for the Internet-of-things (IoT) scenario, optimizing speed/dissipation and suitable for various load and transistor biasing modes. Simulation results confirm the correctness of the proposed approach in meeting specifications, even under Monte Carlo analysis.
JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS
(2021)
Proceedings Paper
Engineering, Electrical & Electronic
Gianluca Giustolisi, Gaetano Palumbo
2018 25TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS)
(2018)
Proceedings Paper
Engineering, Electrical & Electronic
Andrea Ballo, Gianluca Giustolisi, Alfio Dario Grasso, Gaetano Palumbo
2018 25TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS)
(2018)
Article
Engineering, Electrical & Electronic
Tonghui Li, Xiaofeng Duan, Kai Liu, Yongqing Huang
Summary: This paper proposes a hybrid genetic algorithm (HGA) to simplify the process of photodiode parameter extraction and compares its performance with other optimization algorithms. The results show that HGA has better performance in parameter fitting, convergence speed, and accuracy.
MICROELECTRONICS JOURNAL
(2024)
Article
Engineering, Electrical & Electronic
Prachuryya Subash Das, Deepjyoti Deb, Rupam Goswami, Santanu Sharma, Rajesh Saha
Summary: This article proposes the investigation of low power performance of a fin field-effect transistor (FinFET) with surrounding gates using a calibrated technology computer-aided design (TCAD) framework. The study explores the impact of core dimensions and gate edge suppression on the electrical parameters of the device. It is found that reducing the channel length by 35% improves the overall low power performance of the FinFET.
MICROELECTRONICS JOURNAL
(2024)
