Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume 68, Issue 3, Pages 998-1011Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSI.2020.3044454
Keywords
Settling-time; operational transconductance amplifiers; multi-stage amplifiers; feedback amplifiers; CMOS; low-voltage
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This paper analyzes the design approach for three-stage CMOS operational transconductance amplifiers and proposes a design scheme suitable for settling-time specifications. A design example is presented to validate the proposed method.
In this paper we are going to analyze the settling-time in single-, two- and three-stage amplifiers with the intent of deriving approximate but useful design equations that include the effects of the zeros and of the slew-rate limitations. The analysis is mainly devoted to the definition of an approach for the design of three-stage CMOS operational transconductance amplifiers from settling-time specifications. A design example is carried out to validate the proposed approach.
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