Evaluating the use of adder compressors for power-efficient HEVC interpolation filter architecture

Published 2016 View Full Article

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Title
Evaluating the use of adder compressors for power-efficient HEVC interpolation filter architecture
Authors
Keywords
Video coding, HEVC, Hardware architecture, VLSI design, Interpolation filter, Adder compressors
Journal
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
Volume 89, Issue 1, Pages 111-120
Publisher
Springer Nature
Online
2016-05-21
DOI
10.1007/s10470-016-0765-6
References
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