FPGA Investigation on Error-Flare Performance of a Concatenated Staircase and Hamming FEC Code for 400G Inter-Data Center Interconnect

Authors

Keywords

Journal

Volume 37, Issue 1, Pages 188-195

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Online

2018-11-17

DOI

10.1109/jlt.2018.2881924

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