Journal
IEEE ELECTRON DEVICE LETTERS
Volume 39, Issue 12, Pages 1888-1891Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2018.2879543
Keywords
Enhancement-mode GaN MISFETs; self-terminating etching; LPCVD Si3N4; plasma-enhanced atomic layer deposition (PEALD) AlN
Categories
Funding
- National Key Micrometer/Nanometer Processing Laboratory
- Nanofabrication Facility of the Suzhou Institute of Nano-tech and Nano-bionics
Ask authors/readers for more resources
In this letter, we demonstrate a novel PEALD-AlN/LPCVD-Si3N4 dual-gate dielectric employed in enhancement-mode GaN MISFETs, where the gate recess is fabricated based on our proposed self-terminating gate recess etching technique using a GaN cap layer as recess mask. By using LPCVD-Si3N4 and PEALD-AlN dual-gate dielectric layer, the devices exhibit a high-quality gate dielectric and a good GaN channel interface, yielding a high gate swing up to 18 V and a high channel effective mobility of 137 cm(2)/V.s at such high gate bias. Thus, the fabricated devices feature a highmaximumdrain current density of 823mA/mm, a threshold voltage of 2.6 V, an on-resistance of 7.4 Omega . mm, and an ON/OFF current ratio of 10(8) with gate-drain distance of 2 mu m. Meanwhile, a high off-state breakdown voltage of 1290 V is achieved with 10-mu m gate-drain distance. The corresponding specific on-resistance is as low as 1.76 m Omega . cm(2), leading to a high Baliga's figure of merit of 945 MW/cm(2).
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available