Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking

This paper presents a novel technique for the integration of small complementary metal-oxide semiconductor (CMOS) chips into a large area substrate. A key component of the technique is the CMOS chip-based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 mu m larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for microelectromechanical systems micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI Semiconductor's 0.5 mu m CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 and 0.5 mu m, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process. A CMOS/microfluidic hybrid system is also demonstrated based on the proposed integration technology.