An Analysis of Reducing Communication Delay in Network-on-Chip Interconnect Architecture

Title
An Analysis of Reducing Communication Delay in Network-on-Chip Interconnect Architecture
Authors
Keywords
Network-on-Chip (NoC), System-on-Chip (SoC), Mesh, Torus, BFT
Journal
WIRELESS PERSONAL COMMUNICATIONS
Volume 73, Issue 4, Pages 1403-1419
Publisher
Springer Nature
Online
2013-06-10
DOI
10.1007/s11277-013-1257-y

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