Comparison of three single-phase PLL algorithms for UPS applications

In this paper, the performance assessment of three software single-phase phase-locked loop (PLL) algorithms is carried out by means of dynamic analysis and experimental results. Several line disturbances such as phase-angle jump, voltage sag, frequency step, and harmonics are generated by a DSP together with a D/A converter and applied to each PLL. The actual minus the estimated phase-angle values are displayed, providing a refined method for performance evaluation and comparison. Guidelines for parameters adjustments are also presented. In addition, practical implementation issues such as computational delay effects, ride-through, and computational load are addressed. The developed models proved to accurately represent the PLLs under real test conditions.