Design, Optimization, and Scaling of MEM Relays for Ultra-Low-Power Digital Logic

Published 2010 View Full Article

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Title
Design, Optimization, and Scaling of MEM Relays for Ultra-Low-Power Digital Logic
Authors
Keywords
-
Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 58, Issue 1, Pages 236-250
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Online
2010-11-19
DOI
10.1109/ted.2010.2082545

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