FPGA-Based 40.9-Gbits/s Masked AES With Area Optimization for Storage Area Network

Published 2013 View Full Article

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Title
FPGA-Based 40.9-Gbits/s Masked AES With Area Optimization for Storage Area Network
Authors
Keywords
-
Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Volume 60, Issue 1, Pages 36-40
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Online
2013-03-09
DOI
10.1109/tcsii.2012.2234891

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