Write Scheme Allowing Reduced LRS Nonlinearity Requirement in a 3D-RRAM Array With Selector-Less 1TNR Architecture

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Title
Write Scheme Allowing Reduced LRS Nonlinearity Requirement in a 3D-RRAM Array With Selector-Less 1TNR Architecture
Authors
Keywords
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Journal
IEEE ELECTRON DEVICE LETTERS
Volume 35, Issue 2, Pages 223-225
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Online
2014-02-01
DOI
10.1109/led.2013.2294809

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