Journal
IEEE ELECTRON DEVICE LETTERS
Volume 34, Issue 9, Pages 1100-1102Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2013.2274511
Keywords
FinFET/trigate/double-gate; parasitic resistance; schematic FET model; source/drain (S/D) and gate resistance
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We present a schematic transistor model for multifinger multifin FETs, which greatly simplifies an initially complex network. The schematic finFET model accepts various finFET layout information and is accurate in predicting the overall finFET characteristics, including the effect of parasitic resistance (R) and capacitance (C) in a finFET.
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