4.6 Article

Nonvolatile Poly-Si TFT Charge-Trap Flash Memory With Engineered Tunnel Barrier

Journal

IEEE ELECTRON DEVICE LETTERS
Volume 33, Issue 2, Pages 170-172

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2011.2177060

Keywords

High-k; poly-Si thin-film transistor (TFT); system on panel (SOP); TFT; tunnel barrier engineered; VARIOT type

Funding

  1. National Research Foundation of Korea
  2. Ministry of Education, Science and Technology [2011-0004972]

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Tunnel-barrier-engineered thin-film transistor (TFT) memory (TBE-TFT memory) devices on glass substrates were fabricated using low-temperature processes. An amorphous silicon film on the glass substrate was crystallized using excimer laser annealing for system-on-panel applications. The engineered tunnel barrier of VARIOT type (SiO2/Si3N4/SiO2) with a high-k HfO2 charge-trapping layer and an Al2O3 blocking layer was applied to TBE-TFT memory devices in order to enhance the memory performance of TBE-TFT memory devices. As a result, the poly-Si TFT charge-trap Flash memory with an engineered tunnel barrier exhibited excellent memory characteristics, such as large memory window (9.5 V), long retention time, and endurance.

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