Journal
IEEE ELECTRON DEVICE LETTERS
Volume 32, Issue 8, Pages 1086-1088Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2011.2157801
Keywords
Cadmium sulfide (CdS); complementary metal-oxide-semiconductor (CMOS); flexible electronics; pentacene; thin-film transistor (TFT)
Categories
Funding
- Air Force Office of Sponsored Research
- Army Research Laboratory
Ask authors/readers for more resources
In this letter, we demonstrate a fully integrated approach to fabricate cadmium sulfide (CdS)-pentacene complementary metal-oxide-semiconductor (CMOS) digital circuits compatible with flexible electronics. Low-cost and low-temperature chemical bath deposition is used to deposit CdS at 70 degrees C with mobility values > 10 cm(2)/V . s and threshold voltages around 5 V for fully integrated devices. p-MOS thin-film transistors were fabricated using thermally evaporated pentacene as semiconductor with mobility and threshold voltages in the range of 3 x 10(-2) cm(2)/V . s and -3 V, respectively. The CMOS integration approach includes six mask levels with a maximum processing temperature of 100 degrees C.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available