Journal
IEEE ELECTRON DEVICE LETTERS
Volume 31, Issue 12, Pages 1377-1379Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2010.2080256
Keywords
Bulk gate-all-around silicon nanowire MOSFETs (GAA NWFETs); parasitic effects; stress-limited oxidation; volume inversion
Categories
Funding
- special funds for the National Basic Research Program of China (973 Program)
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In this letter, a novel self-aligned CMOS-compatible method for the fabrication of gate-all-around silicon nanowire MOSFETs (GAA SNWFETs) on bulk substrate has been proposed. The fabricated SNWFET featuring 33-nm gate length and 7-nm diameter shows the highest driving current (I-on = 2500 mu A/mu m at V-ds = V-gs = 1.0 V) among previously reported data and achieves high I-on/I-off ratio of 10(5), lightening the promise for high performance and strong scalability of GAA SNWFETs. The process details and optimization procedure are extensively discussed.
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