4.6 Article

Improved high temperature retention for charge-trapping memory by using double quantum barriers

Journal

IEEE ELECTRON DEVICE LETTERS
Volume 29, Issue 4, Pages 386-388

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2008.917811

Keywords

erase; high-k; nonvolatile memory; program

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We have fabricated the [TaN-Ir3Si]-HfAlO-LaAlO3-Hf0.3O0.5N0.2-HfAlO-SiO2-Si double quantum-barrier charge-trapping memory device. Under fast 100 mu s and low +/- 8 V program/erase (P/E) condition, an initial memory window of 2.6 V and good extrapolated ten-year retention window of 1.9 V are achieved at 125 degrees C. Very small P/E retention decays of 64/22 mV/dec at 125 degrees C are measured due to double quantum barriers to confine the charges in deep-trapping-energy Hf0.3O0.5N0.2 well.

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