Wiring Effect Optimization in 65-nm Low-Power NMOS

Published 2008 View Full Article

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Title
Wiring Effect Optimization in 65-nm Low-Power NMOS
Authors
Keywords
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Journal
IEEE ELECTRON DEVICE LETTERS
Volume 29, Issue 11, Pages 1245-1248
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Online
2008-09-30
DOI
10.1109/led.2008.2005515

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