3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections

Published 2010 View Full Article

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Title
3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections
Authors
Keywords
-
Journal
IBM JOURNAL OF RESEARCH AND DEVELOPMENT
Volume 52, Issue 6, Pages 611-622
Publisher
IBM
Online
2010-04-06
DOI
10.1147/jrd.2008.5388567

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