Reliable high-yield CNTFET-based 9T SRAM operating near threshold voltage region

A Charge-Recycling Assist Technique for Reliable and Low Power SRAM Design

(2016) Woong Choi et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

Quasi-ballistic carbon nanotube array transistors with current density exceeding Si and GaAs

(2016) G. J. Brady et al.   Science Advances

Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations

(2015) Gage Hills et al.   IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

A Novel Robust and Low-Leakage SRAM Cell With Nine Carbon Nanotube Transistors

(2015) Yanan Sun et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist

(2014) Nan-Chun Lien et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors

(2014) Dao-Ping Wang et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

Carbon Nanotubes Blowing New Life Into NP Dynamic CMOS Circuits

(2013) Yanan Sun et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

(2012) Ming-Hsien Tu et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

Carbon Nanotube SRAM Design With Metallic CNT or Removed Metallic CNT Tolerant Approaches

(2012) Zhe Zhang et al.   IEEE TRANSACTIONS ON NANOTECHNOLOGY

Process variations aware area efficient negative bit-line voltage scheme for improving write ability of SRAM in nanometer technologies

(2012) A. Goel et al.   IET Circuits Devices & Systems

A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM)

(2011) Adam Teman et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design

(2010) Rajiv V. Joshi et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

A Voltage Scalable 0.26 V, 64 kb 8T SRAM With V$_{\min}$ Lowering Techniques and Deep Sleep Mode

(2009) Tae-Hyoung Kim et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS

(2009) Ik Joon Chang et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

Design of a CNTFET-Based SRAM Cell by Dual-Chirality Selection

(2009) Sheng Lin et al.   IEEE TRANSACTIONS ON NANOTECHNOLOGY

An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches

(2008) Leland Chang et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

High-Performance Low-Power Selective Precharge Schemes for Address Decoders

(2008) M.A. Turi et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

Accurate Estimation of SRAM Dynamic Stability

(2008) DiaaEldin Khalil et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Characterization of a Novel Nine-Transistor SRAM Cell

(2008) Zhiyu Liu et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS