Journal
ELECTRONICS LETTERS
Volume 47, Issue 9, Pages 530-531Publisher
INST ENGINEERING TECHNOLOGY-IET
DOI: 10.1049/el.2011.0063
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Funding
- NSF CDADIC
- NSF [ECCS-0845849]
- Div Of Electrical, Commun & Cyber Sys
- Directorate For Engineering [0845849] Funding Source: National Science Foundation
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Current-reuse and gate-modulation techniques have been presented for ultra-low power and low phase noise quadrature voltage-controlled oscillator (QVCO) design. The proposed topology overcomes the trade-off between low phase noise and low power consumption. Results demonstrate a phase noise of -123.7 dBc/Hz at 1 MHz offset while consuming only 680 uW (including output buffers) with a 1.1 V supply.
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