High-level interconnect model for the quantum logic array architecture

Published 2008 View Full Article

  1. Home
  2. Publications
  3. Publication Search
  4. Publication Details
Title
High-level interconnect model for the quantum logic array architecture
Authors
Keywords
-
Journal
ACM Journal on Emerging Technologies in Computing Systems
Volume 4, Issue 1, Pages 1-28
Publisher
Association for Computing Machinery (ACM)
Online
2008-04-08
DOI
10.1145/1330521.1330522

Ask authors/readers for more resources

Protocol

Community support

Reagent

Community support

Reprint

Contact the author

Publish scientific posters with Peeref

Peeref publishes scientific posters from all research disciplines. Our Diamond Open Access policy means free access to content and no publication fees for authors.

Learn More

Become a Peeref-certified reviewer

The Peeref Institute provides free reviewer training that teaches the core competencies of the academic peer review process.

Get Started
Webinars Posters Questions Hubs Funding Journals Articles Connect Collections Reviewers About Us FAQs Mobile App Privacy Policy Terms of Use
© Peeref 2019-2024. All rights reserved.