4.6 Article

Reconfigurable Codesign of STT-MRAM Under Process Variations in Deeply Scaled Technology

Journal

IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 62, Issue 6, Pages 1769-1777

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2015.2412960

Keywords

Magnetic tunnel junction (MTJ); nonvolatile memory; process variations; reconfigurable design; spin-transfer torque magnetic random access memory (STT-MRAM)

Funding

  1. National Natural Science Foundation of China [61471015]
  2. French National Agency through the ANR-MARS Project

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Recently, spin-transfer torque magnetic random access memory (STT-MRAM) has been considered as a promising universal memory candidate for future memory and computing systems, thanks to its nonvolatility, high speed, low power, good endurance, and scalability. However, as technology scales down, STT-MRAM suffers from serious process variations and thermal fluctuations, which greatly degrade the performance and stability of STT-MRAM. In general, the optimization and robustness of STT-MRAM under process variations often require a hybrid design flow and multilevel codesign strategies. In this paper, we quantitatively analyze the impacts of process variations and thermal fluctuations on the STT-MRAM performances from physics, technology, and circuit design point of views. Based on the analyses, we found that readability is becoming the newest challenge for deeply scaled STT-MRAM due to the conflict between sensing margin and read disturbance. To deal with this problem, a novel reconfigurable design strategy from device, circuit, and architecture codesign perspective is then presented. Finally, a conceptual hybrid magnetic/CMOS design flow is also proposed for STT-MRAM in deeply scaled technology nodes.

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