4.5 Article

Phase-Change Memory Optimization for Green Cloud with Genetic Algorithm

Journal

IEEE TRANSACTIONS ON COMPUTERS
Volume 64, Issue 12, Pages 3528-3540

Publisher

IEEE COMPUTER SOC
DOI: 10.1109/TC.2015.2409857

Keywords

Phase-change memory; task scheduling; MLC; SLC; genetic algorithm; green cloud

Funding

  1. NSF [CNS-1457506, CNS-1359557, GD: 10351806001000000]
  2. National Natural Science Foundation of China (NSFC) [61170077]
  3. ST project [GDA:2012B091100198, SZ JCYJ20130326110956468]
  4. US National Science Foundation [CNS-1305359]
  5. Division Of Computer and Network Systems
  6. Direct For Computer & Info Scie & Enginr [1457506] Funding Source: National Science Foundation
  7. Division Of Computer and Network Systems
  8. Direct For Computer & Info Scie & Enginr [1305359] Funding Source: National Science Foundation

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Green cloud is an emerging new technology in the computing world in which memory is a critical component. Phase-change memory (PCM) is one of the most promising alternative techniques to the dynamic random access memory (DRAM) that faces the scalability wall. Recent research has been focusing on the multi-level cell (MLC) of PCM. By precisely arranging multiple levels of resistance inside a PCM cell, more than one bit of data can be stored in one single PCM cell. However, the MLC PCM suffers from the degradation of performance compared to the single-level cell (SLC) PCM, due to the longer memory access time. In this paper, we present a genetic-based optimization algorithm for chip multiprocessor (CMP) equipped with PCM memory in green clouds. The proposed genetic-based algorithm not only schedules and assigns tasks to cores in the CMP system, but also provides a PCM MLC configuration that balances the PCM memory performance as well as the efficiency. The experimental results show that our genetic-based algorithm can significantly reduce the maximum memory usage by 76.8 percent comparing with the uniform SLC configuration, and improve the efficiency of memory usage by 127 percent comparing with the uniform 4 bits/cell MLC configuration. Moreover, the performance of the system is also improved by 24.5 percent comparing with the uniform 4 bits/cell MLC configuration in terms of total execution time.

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