Article
Computer Science, Hardware & Architecture
He-Teng Zhang, Masahiro Fujita, Chung-Kuan Cheng, Jie-Hong R. Jiang
Summary: The new bus routing framework proposed in the study, based on maze routing and Boolean satisfiability, quickly produces high-quality results in integrated circuit design. Experiments show the framework is faster than previous methods and improves overall cost by 12% while minimizing spacing violations.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
(2021)
Article
Computer Science, Hardware & Architecture
Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Bill Lin, Dongwon Park
Summary: The article introduces a SMT-based CFET SDC synthesis framework that optimizes layouts by solving place-and-route at the block level, achieving smaller cell area and metal length. Constraints and objectives are used to reduce DRVs at the block level for improved routability, while DTCO exploration helps achieve smaller block-level areas.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
(2021)
Article
Computer Science, Hardware & Architecture
Daeyeal Lee, Dongwon Park, Chia-Tung Ho, Ilgweon Kang, Hayoung Kim, Sicun Gao, Bill Lin, Chung-Kuan Cheng
Summary: This article proposes an automated standard cell synthesis framework, SP&R, which utilizes multiobjective optimization to achieve optimal cell layouts, and improves runtime efficiency by developing various search-space reduction techniques. The framework successfully generates a 7-nm standard cell library by orchestrating innovative tactics to produce improved cell size and track numbers compared to known layouts.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
(2021)
Article
Mathematics, Applied
Pengwen Chen
Summary: In this paper, the RAAR algorithm is analyzed from an optimization perspective. The algorithm is based on the alternating direction method of multipliers and uses dual iteration and penalty parameter alteration to search for local saddles in the primal-dual space, avoiding stagnation and selecting fixed points.
Article
Computer Science, Hardware & Architecture
Daeyeal Lee, Bill Lin, Chung-Kuan Cheng
Summary: The letter proposes an SMT-based framework for finding contention-free task mapping with the minimum application schedule length. Through SMT's fast reasoning capability for conditional constraints and efficient search-space reduction techniques, practical scalability is achieved. Experiments show that the approach achieves higher scalability and faster runtime compared to ILP approach.
IEEE EMBEDDED SYSTEMS LETTERS
(2021)
Article
Computer Science, Hardware & Architecture
Chung-Kuan Cheng, Andrew B. Kahng, Hayoung Kim, Minsoo Kim, Daeyeal Lee, Dongwon Park, Mingyu Woo
Summary: In advanced nodes, scaling boosters are explored to improve power, performance, area, and cost in new technologies, but they also increase complexity of standard-cell architectures and design enablement. Design-technology co-optimization (DTCO) methodologies are required to evaluate the benefits of scaling boosters. This study presents a new framework for evaluating intrinsic routability across technology and design choices, enabling faster and more comprehensive evaluation of technology options early in the development process.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
(2022)
Article
Computer Science, Hardware & Architecture
Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz, Daeyeal Lee, Bill Lin
Summary: As technology nodes advance, geometric pitch scaling slows down. To continue scaling, DTCO and STCO are introduced, using pitch scaling, patterning, and novel structures. However, the iterative process becomes a bottleneck due to physical layout considerations. This study proposes a machine learning model that predicts the sensitivity of minimum valid block-level area, improving the efficiency and robustness of DTCO and STCO explorations.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
(2022)
Article
Computer Science, Hardware & Architecture
Uday Mallappa, Chung-Kuan Cheng, Bill Lin
Summary: This article proposes a joint application-aware oblivious routing and static virtual channel allocation framework to achieve better deadlock-free performance in on-chip interconnection networks.
IEEE DESIGN & TEST
(2022)
Article
Computer Science, Hardware & Architecture
Uday Mallappa, Chung-Kuan Cheng, Bill Lin
Summary: This letter proposes a joint application-aware oblivious routing and static VC allocation framework, which optimally solves both problems together and achieves better deadlock-free performance.
IEEE EMBEDDED SYSTEMS LETTERS
(2022)
Article
Computer Science, Artificial Intelligence
Janith Wijesinghe, Pengwen Chen
Summary: Optimal transport is used to solve point set matching problems by recovering the point-to-point correspondence. It is a form of linear programming with dense constraints. Interior point methods can handle linear programming if accurate computation of ill-conditioned Hessians is feasible. Matrix balancing is employed to compute optimal transport under entropy regularization approaches, with solution quality relying on accurate matrix balancing and boundedness of the dual vector. This study applies sparse support constraints to matrix-balancing based interior point methods, iteratively updating the sparse set to truncate the domain of the transport plan and ensuring the existence of matrix balancing and boundedness of the dual vector.
SIAM JOURNAL ON IMAGING SCIENCES
(2023)
Proceedings Paper
Computer Science, Theory & Methods
Pengwen Chen, Chung-Kuan Cheng, Albert Chern, Chester Holtz, Aoxi Li, Yucheng Wang
Summary: This research proposes an algorithm based on QCQP to find initial layouts with minimal wirelength under density and fixed-macro constraints. It also introduces an efficient sequential quadratic programming algorithm and a sub-space method to improve the quality of solutions. The experiments demonstrate that combining the initial layouts produced by this algorithm with a global analytical placer can significantly improve wirelength.
PROCEEDINGS OF THE 2023 INTERNATIONAL SYMPOSIUM ON PHYSICAL DESIGN, ISPD 2023
(2023)
Article
Computer Science, Information Systems
Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Bill Lin
Summary: Continued scaling according to Moore's law is becoming more difficult due to limitations in standard cell device scaling. Expanding in the third dimension via monolithic 3D integration could be a solution, but it also creates new challenges. This article presents three baby steps to alleviate the pin density problem and demonstrates their potential benefits for footprint scaling.
Article
Computer Science, Hardware & Architecture
Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Bill Lin
Summary: This article proposes a CFET-based cell synthesis framework that optimizes cell and block-level area by redesigning the multirow structure and addressing routing issues simultaneously. Experimental results demonstrate that MR 2.5T CFET outperforms traditional 3.5T CFET in terms of area and wirelength.
IEEE JOURNAL ON EXPLORATORY SOLID-STATE COMPUTATIONAL DEVICES AND CIRCUITS
(2021)
Article
Computer Science, Hardware & Architecture
Daeyeal Lee, Chia-Tung Ho, Ilgweon Kang, Sicun Gao, Bill Lin, Chung-Kuan Cheng
Summary: This article introduces a novel SMT-based many-tier VFET standard cell synthesis framework to achieve maximum PPAC benefits through simultaneous placement and routing. By improving pin-accessibility and reducing vertical routing, our concurrent P&R achieves a smaller cell area compared to the conventional sequential P&R approach, with an average reduction of 15.2% for 2-tier VFET. Through extensive exploration of many-tier VFET configurations up to 4-tier, it is shown that the 4-tier VFET respectively achieves significant area reduction on chip-level and block-level.
IEEE JOURNAL ON EXPLORATORY SOLID-STATE COMPUTATIONAL DEVICES AND CIRCUITS
(2021)
Article
Mathematics, Applied
Pengwen Chen, Chung-Kuan Cheng, Xinyuan Wang
Summary: The study introduces a stability preserved Arnoldi algorithm for matrix exponential in the time domain simulation of large-scale power delivery networks, utilizing the range and null space of the system operator. By modifying the orthogonality in the Krylov subspace and adjusting the numerical ranges, theoretical convergence analysis for computing phi-functions is obtained. Simulations on RLC networks demonstrate the effectiveness of the Arnoldi algorithm.
SIAM JOURNAL ON NUMERICAL ANALYSIS
(2021)