A Charge Recycling SAR ADC With a LSB-Down Switching Scheme

This paper presents a new energy efficient successive approximation analog-to-digital converter (ADC) using a charge recycling and LSB-down switching scheme for the capacitive digital-to-analog converter (CDAC). Compared to the conventional binary weighed CDAC, the proposed technique exhibits a 95% reduction in switching energy, a 50% reduction in capacitor area, and with 30% reduction in nonlinearity under the same unit capacitor size and matching condition. The improvement on the switching energy consumption is the best among reported CDAC switching techniques. To validate the technique, a prototype of 10-bit ADC is fabricated in a 0.13 mu m CMOS technology using standard capacitors. With a unit capacitor size of 30 fF, the ADC consumes 15.6 mu W from a 0.5 V digital supply and a 1 V analog supply. The measured signal-to-noise-plus-distortion ratio is 54.6 dB at 1.1 MS/s. The FOM is 31.8 fJ/conv.-step, which is among the best when normalized to the same unit capacitor size.