340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS

Authors

Keywords

Journal

Volume 50, Issue 4, Pages 1048-1058

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Online

2015-01-24

DOI

10.1109/jssc.2014.2384039

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