Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 50, Issue 11, Pages 2645-2654Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2015.2466475
Keywords
20 nm CMOS; analog-to-digital converter (ADC); IEEE 802.11ac; low cost; low power; redundancy; successive approximation register (SAR)
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This paper presents a low-cost successive approximation register (SAR) analog-to-digital converter (ADC) for IEEE 802.11 ac applications. In this paper, a binary-scaled recombination capacitor weighting method is disclosed. The digital sub-blocks in this ADC are composed of standard library logic cells. The prototype is fabricated in a 1P8M 20 nm CMOS technology. At 0.9 V supply and 160 MS/s, the ADC consumes 0.68 mW. It achieves an SNDR of 57.7 dB and 57.13 dB at low and Nyquist input frequency, respectively, resulting in figures of merit (FoMs) of 6.8 and 7.3 fJ/conversion-step, respectively. At 1 V supply and 320 MS/s, the ADC consumes 1.52 mW. It achieves an SNDR of 57.1 dB and 50.89 dB at low and Nyquist input frequency, respectively, resulting in FoMs of 8.1 and 16.5 fJ/conversion-step, respectively. The ADC core only occupies an active area of 33 mu m x 35 mu m.
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