Suppression in the electrical hysteresis by using CaF2 dielectric layer for p-GaN MIS capacitors

The capacitance-voltage (C-V) hysteresis in the bidirectional measurements of the p-GaN metal-insulator-semiconductor (MIS) capacitor is suppressed by using a CaF2 dielectric layer and a post annealing treatment. The density of trapped charge states at the CaF2/p-GaN interface is dramatically reduced from 1.3 x 10(13) cm(2) to 1.1 x 10(11)/cm(2) compared to that of the Al2O3/p-GaN interface with a large C-V hysteresis. It is observed that the disordered oxidized interfacial layer can be avoided by using the CaF2 dielectric. The downward band bending of p-GaN is decreased from 1.51 to 0.85 eV as a result of the low-density oxides-related trap states. Our work indicates that the CaF2 can be used as a promising dielectric layer for the p-GaN MIS structures. Published by AIP Publishing.