Power-Rail ESD Clamp Circuit with Parasitic-BJT and Channel Parallel Shunt Paths to Achieve Enhanced Robustness

Authors

Keywords

Journal

Volume E100.C, Issue 3, Pages 344-347

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Online

2017-03-01

DOI

10.1587/transele.e100.c.344

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