Article
Multidisciplinary Sciences
Saeedeh Akbari Rokn Abadi, Amirhossein Mohammadi, Somayyeh Koohi
Summary: In this study, a novel image-based encoding method called WalkIm is proposed for the classification of biological sequences. Compared to existing methods, WalkIm achieves competitive accuracy and superior efficiency without the need for parameter initialization or network architecture adjustment. Additionally, WalkIm exhibits high-speed convergence and reduced network complexity. The compatibility of WalkIm with free-space optical processing technology is also addressed, leading to a significant reduction in training time and preservation of image structure.
Article
Computer Science, Artificial Intelligence
Hui Zhang, Quanming Yao, James T. Kwok, Xiang Bai
Summary: In this article, the authors propose a method based on neural architecture search to optimize the performance of text recognition tasks by searching for suitable feature extractors. They design a domain-specific search space and use a two-stage algorithm to effectively search within it. The proposed method is compared with state-of-the-art approaches on hand-written and scene text recognition tasks, and the results demonstrate better recognition performance with lower latency.
IEEE TRANSACTIONS ON PATTERN ANALYSIS AND MACHINE INTELLIGENCE
(2023)
Article
Multidisciplinary Sciences
Wentao Zhao, Dalin Zhou, Xinguo Qiu, Wei Jiang
Summary: This study tested 7 different models on 3 datasets to compare their performance in art classification with or without transfer learning, achieving state-of-the-art results through optimized model structures. Teaching computers to classify art improves performance, and visualizing the classification process helps understand the challenges encountered.
Article
Computer Science, Artificial Intelligence
Hamdan Abdellatef, Mohamed Khalil-Hani, Nasir Shaikh-Husin, Sayed Omid Ayat
Summary: CNNs excel in recognition tasks but are computationally intensive, while SC offers an alternative with lower power consumption and high accuracy; experimental results demonstrate that SC-based CNNs achieve high classification accuracy across various datasets.
Article
Computer Science, Artificial Intelligence
Christiam F. Frasser, Pablo Linares-Serrano, Ivan Diez de los Rios, Alejandro Moran, Erik S. Skibinsky-Gitlin, Joan Font-Rossello, Vincent Canals, Miquel Roca, Teresa Serrano-Gotarredona, Josep L. Rossello
Summary: The study proposes a power-and-area efficient architecture for edge artificial intelligence based on stochastic computing, which addresses the drawbacks of deep learning techniques in edge computing devices. The embedded CNN in the FPGA chip shows better performance compared to traditional binary logic and other stochastic computing implementations. In addition, the proposed design demonstrates better overall characteristics in VLSI synthesis.
IEEE TRANSACTIONS ON NEURAL NETWORKS AND LEARNING SYSTEMS
(2023)
Article
Computer Science, Information Systems
Ning Mao, Haigang Yang, Zhihong Huang
Summary: In this paper, a parameterized design approach is proposed to explore the maximum parallelism in implementing CNN algorithms on FPGA. A hardware library is established to accommodate various CNN models, and an algorithm is proposed to find the optimal level of parallelism. The case study shows that our design achieves higher FPS and lower latency with fewer LUTs and FFs compared to existing high-level synthesis designs.
Article
Engineering, Electrical & Electronic
Mingqiang Huang, Yucen Liu, Changhai Man, Kai Li, Quan Cheng, Wei Mao, Hao Yu
Summary: In this work, a state-of-the-art multi-bit-width accelerator is developed for efficiently processing multi-bit-width convolutional neural networks. A differential Neural Architecture Search method is adopted for generating high-accuracy multi-bit-width networks, and a hybrid Booth based multi-bit-width multiply-add-accumulation unit is developed for data processing. Additionally, a vector systolic array is proposed for accelerating matrix multiplications. The practical deployment on FPGA platform demonstrates high performance.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
(2022)
Article
Chemistry, Multidisciplinary
Zhengjin Weng, Haofei Zheng, Wei Lei, Helong Jiang, Kah-Wee Ang, Zhiwei Zhao
Summary: This study demonstrates the successful fabrication of high-yield, high-performance, and uniform memristors using a single-crystalline few-layered manganese phosphorus trisulfide (MnPS3) as a resistive switching medium. The memristors exhibit desired characteristics for neuromorphic computing and achieve a high accuracy of 95.15% in supervised learning using the MNIST handwritten recognition dataset. This research is significant for experimental studies on memristors.
ADVANCED FUNCTIONAL MATERIALS
(2023)
Article
Computer Science, Information Systems
Paola Busia, Svetlana Minakova, Todor Stefanov, Luigi Raffo, Paolo Meloni
Summary: The study introduces a flexible, user-friendly, and accurate method for evaluating CNN design on embedded edge-processing systems, significantly improving evaluation accuracy.
Article
Computer Science, Artificial Intelligence
Luke Kljucaric, Alan D. George
Summary: As computer architectures integrate application-specific hardware, understanding the relative performance of devices becomes crucial. Benchmarking suites like MLPerf aim to standardize fair comparisons of different hardware architectures, but many apps require different workloads and have specific performance goals. This research analyzes compute architectures for handwritten Chinese character recognition, comparing latency and throughput for different models using ML-specific hardware.
ACM TRANSACTIONS ON INTELLIGENT SYSTEMS AND TECHNOLOGY
(2023)
Article
Chemistry, Analytical
Duc Khai Lam, Cam Vinh Du, Hoai Luan Pham
Summary: Lane detection is a fundamental problem in autonomous vehicles, and deep learning models have achieved high accuracy for this task. However, existing methods face challenges in post-processing and real-time speed. To address these issues, this paper proposes a lightweight convolutional neural network that requires minimal post-processing and achieves high accuracy on the TuSimple dataset. A hardware accelerator is also implemented to optimize processing time and power consumption, achieving a high computation throughput and energy efficiency.
Article
Computer Science, Artificial Intelligence
Yirong Xie, Hong Chen, Yongjie Ma, Yang Xu
Summary: Evolutionary Neural Architecture Search (ENAS) is an automated method for designing deep network architecture, which has gained extensive attention in the field of automated machine learning. This paper proposes improvements in two aspects: the introduction of efficient CNN-based building blocks and a triplet attention mechanism to enhance the effectiveness and classification performance of the generated architectures, and the use of a random forest-based performance predictor to reduce computation in training. Experimental results demonstrate that the proposed algorithm significantly reduces computational resources while achieving competitive classification performance on the CIFAR dataset.
Article
Computer Science, Information Systems
Dongyang Zhang, Jie Shao, Zhenwen Liang, Lianli Gao, Heng Tao Shen
Summary: This study introduces a cascaded super-resolution convolutional neural network (CSRCNN) to address the aliasing artifacts and high computational costs caused by existing methods that use interpolation during the beginning stage. Experimental results show that the proposed network achieves superior performance, especially with an 8x upsampling factor.
IEEE TRANSACTIONS ON MULTIMEDIA
(2021)
Article
Chemistry, Analytical
Xiaoru Xie, Mingyu Zhu, Siyuan Lu, Zhongfeng Wang
Summary: Recently, the layer-wise N:M fine-grained sparse neural network algorithm has gained significant attention for its ability to reduce computational complexity without sacrificing accuracy. However, without proper hardware support, the full potential of this algorithm cannot be realized. In this study, we introduce an efficient accelerator for N:M sparse CNNs with layer-wise sparse patterns. By analyzing different processing element structures and incorporating variable sparse convolutional dimensions, our hardware design achieves efficient acceleration of CNNs. Through evaluation with classical CNNs, our design demonstrates superior power efficiency compared to existing accelerators for structured and unstructured pruned networks.
Article
Engineering, Electrical & Electronic
Yuehai Chen, Yijun Liu, Wujian Ye, Chin-Chen Chang
Summary: This paper proposes a high-performance general spiking convolution processing unit and hardware architecture for efficient computation of deep spiking neural networks. Experimental results show that the proposed FPGA-based processor can effectively deploy different large-scale SNNs models, achieving higher recognition accuracies, faster inference speed, and lower power consumption compared to existing processors.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
(2023)