RF SOI CMOS technology on 1st and 2nd generation trap-rich high resistivity SOI wafers

Title

RF SOI CMOS technology on 1st and 2nd generation trap-rich high resistivity SOI wafers

Authors

Keywords

High-resistivity (HR) SOI substrate, Trap-rich high-resistivity silicon, Enhanced signal integrity silicon-on-insulator (eSI HR-SOI), Substrate effective resistivity, Silicon-on-insulator, DC and RF performance, Partially-depleted (PD) SOI MOSFETs, Crosstalk, Digital substrate noise

Journal

SOLID-STATE ELECTRONICS

Volume 128, Issue -, Pages 121-128

Publisher

Elsevier BV

Online

2016-10-19

DOI

10.1016/j.sse.2016.10.035