Journal
JOURNAL OF THE ELECTROCHEMICAL SOCIETY
Volume 165, Issue 4, Pages H3051-H3060Publisher
ELECTROCHEMICAL SOC INC
DOI: 10.1149/2.0081804jes
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Funding
- Defense research and development organization (DRDO) [ERIP/ER/10003866/M/01/1388]
- CSIR [09/137/(558)/2015-EMR-I]
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Impact of rapid thermal (RT) annealing and normal selenization process on the properties of CuInSe2 (CIS) layers prepared by electrochemical route is reported. Cyclic voltammetric measurement was carried out to optimize the co-deposition potentials. A range of characterization techniques were employed to study the properties. Three prominent reflections (112),(204/220) and (312/116) of tetragonal CIS were exhibited in as-deposited CIS layers. Upon selenization, the crystallinity was found to be improved. Uniform, compact, densely packed surface morphology was observed in as-prepared sample. Large grains are developed upon RT annealing due to recrystallization. Elemental composition obtained by EDAX confirms the growth of stoichiometric layers. Photo-electrochemical study demonstrates the p-type conductivity. Current-voltage, capacitance-voltage, electrochemical impedance spectroscopy were conducted to investigate the influence of the grain size and crystallinity on electrical properties. Energy band-gap estimated from absorption spectra were 1.18, 1.04 and 0.98 eV for as-deposited, selenized, RT annealed samples, respectively. X-ray Photoelectron spectroscopy confirms the presence of Cu+, In3+ and Se2- e- oxidation states in all CIS layers. Power conversion efficiency of 3.05% and 5.94% were achieved for selenized and RT annealed samples, respectively. The improved efficiency measured for RT annealed sample is proposed due to the growth of highly crystalline, large grain and compact surface morphology. (C) The Author(s) 2017. Published by ECS.
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