Carbon Nanotube Field Effect Transistor Switching Logic for Designing Efficient Ternary Arithmetic Circuits

Novel high-efficiency ternary arithmetic circuits using carbon nanotube field effect transistors (CNFETs) are presented in this paper. In the ternary logic, compared to binary logic, the number of interconnections and the amount of charging of wires are decreased which can lead to lower power and area consumption in VLSI chips. The adjustable threshold voltage of CNFET, makes it a suitable choice for being used in the ternary logic designs. All of the proposed circuits are designed based on switching logic method. First, a ternary successor-predecessor, a half adder, and a multiplier are presented and then a ternary full adder and a 3-trit multiplier are presented. The presented ternary circuits have high driving capability and are robust as well. Synopsys HSPICE simulator with the Stanford 32 nm-CNFET technology are used for simulations. The average power consumption, static power, delay, and energy of the proposed designs are significantly lower than other conventional and state-of-the-art CNFET-based ternary circuits. In addition, the proposed ternary full adder is applied in a ternary ripple carry adder structure to demonstrate the efficiency of the proposed circuits. The utilization of the proposed ternary circuits based on the switching logic results in over 60% reductions in terms of the energy as compared to the CNFET-based ternary logic and arithmetic circuits, recently proposed in the literature.