FPGA Hardware Acceleration of a Phylogenetic Tree Reconstruction with Maximum Parsimony Algorithm

Published 2017 View Full Article

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Title
FPGA Hardware Acceleration of a Phylogenetic Tree Reconstruction with Maximum Parsimony Algorithm
Authors
Keywords
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Journal
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
Volume E100.D, Issue 2, Pages 256-264
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Online
2017-02-01
DOI
10.1587/transinf.2015edp7433

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