Article
Engineering, Electrical & Electronic
Farzin Mahboob Sardroudi, Mehdi Habibi, Mohammad Hossein Moaiyeri
Summary: The paper proposes a dynamic ternary full adder using CNFETs, which has lower power consumption and greater robustness. Through simulation verification, the performance of this method is shown to be superior to previous ternary adders under different conditions.
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS
(2021)
Article
Engineering, Electrical & Electronic
Farzin Mahboob Sardroudi, Mehdi Habibi, Mohammad Hossein Moaiyeri
Summary: This paper introduces a ternary half adder and a 1-trit multiplier designed using carbon nanotube transistors, which have advantages over MOSFETs and provide lower power consumption, delay, and transistor count. The proposed circuits exhibit robust performance over a wide range of operating conditions, with improved efficiency compared to previous designs.
MICROELECTRONICS JOURNAL
(2021)
Article
Computer Science, Information Systems
S. Ratankumar, L. Koteswara Rao, M. Kiran Kumar
Summary: A three-input logic circuit design using carbon nanotube field effect transistors (CNTFETs) is presented, utilizing ternary logic and optimizing for reduced delay times. The design showed a significant reduction in delay times, but power dissipation was not optimized, making it suitable for various Boolean circuits.
CMC-COMPUTERS MATERIALS & CONTINUA
(2022)
Article
Engineering, Electrical & Electronic
Shaik Javid Basha, P. Venkatramana
Summary: This paper discusses the design of ternary digital circuits, focusing on the use of graphene nanoribbon field effect transistors (GNRFETs) and resistive random access memory (RRAM). The proposed circuits show improved performance compared to carbon nanotube FETs (CNTFETs) and RRAM-based circuits. The effects of line edge roughness (P-r) and process, voltage, and temperature (PVT) variations on circuit performance are also analyzed. The results demonstrate the advantages of using ternary logic and the potential for further optimization in circuit design.
CIRCUITS SYSTEMS AND SIGNAL PROCESSING
(2023)
Article
Computer Science, Hardware & Architecture
Mohammad-Ali Asadi, Mohammad Mosleh, Majid Haghparast
Summary: Integrated circuits face challenges of heat and area occupation, with strategies like reversible circuits and multiple-valued logic proving effective. Efficient use of multiple-valued logic capabilities is key to reducing complexity and delays in computational circuits. The proposed reversible circuits show superiority in quantum cost despite similarities in other criteria with previous designs.
JOURNAL OF SUPERCOMPUTING
(2021)
Article
Engineering, Electrical & Electronic
Jongbeom Kim, Hyundong Lee, Jonghyun Ko, Bongjun Kim, Taigon Song
Summary: This paper presents a practical design methodology and a set of novel ternary logic based on inkjet-printed anti-ambipolar transistors (AATs) and CMOSs. Balanced ternary full adders and two design methodologies for ternary logic are proposed. Additionally, an optimization methodology for inkjet-printed ternary circuit stability is introduced.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
(2023)
Article
Engineering, Electrical & Electronic
Mohammad Khaleqi Qaleh Jooq, Mohammad Hossein Moaiyeri, Khalil Tamersit
Summary: Ternary logic has been studied for decades and offers advantages in reducing interconnects and operation complexity, but existing ternary logic gates have too many transistors. The authors propose ultra-compact ternary logic gates based on the negative capacitance feature of ferroelectric materials and carbon nanotube field-effect transistors. Simulation results show correct and robust functionality, with significant improvements in transistor count, area, and energy-delay product compared to previous state-of-the-art ternary gates.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
(2021)
Article
Computer Science, Hardware & Architecture
Trapti Sharma, Laxmi Kumre
Summary: This study introduces a method for designing asynchronous and synchronous counters using three valued logic, with optimized circuit implementation in carbon nanotube technology. Performance evaluation using Synopsys HSPICE simulator shows significant reduction in power consumption and Power delay product for both counters.
COMPUTERS & ELECTRICAL ENGINEERING
(2021)
Article
Engineering, Electrical & Electronic
Erfan Abbasian, Maedeh Orouji, Sana Taghipour Anvari
Summary: This paper presents a novel ternary Half-Adder (THA) design implemented with metal-oxide semiconductor (MOS)-type graphene nanoribbon field-effect transistor (GNRFET). The proposed design significantly reduces transistor count, improves power and energy consumption, and shows superior performance compared to existing THA circuits. The proposed THA is also compared with a carbon nanotube field-effect transistor (CNTFET)-based counterpart, demonstrating lower power and energy consumption, although with a slightly longer delay.
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS
(2023)
Article
Engineering, Electrical & Electronic
Abhay S. Vidhyadharan, Kasthuri Bha, Sanjay Vidhyadharan
Summary: This paper presents a carbon nanotube FET-based ultra-low-power dualVDD ternary half adder circuit, which significantly reduces power dissipation compared to conventional designs and has lower delays. The proposed design consumes significantly less power and exhibits lower delays compared to other CNFET and CMOS ternary half adder designs.
CIRCUITS SYSTEMS AND SIGNAL PROCESSING
(2021)
Article
Computer Science, Theory & Methods
Zarin Tasnim Sandhie, Jill Arvindbhai Patel, Farid Uddin Ahmed, Masud H. Chowdhury
Summary: Computing technologies are currently based on binary logic/number system, but there is a strong push to move towards a higher radix logic/number system to overcome the limitations of binary system as data processing needs increase. This push is motivated by anticipated saturation of Moore's law and the necessity to increase information density and processing speed in future micro and nanoelectronic circuits and systems.
ACM COMPUTING SURVEYS
(2021)
Article
Engineering, Electrical & Electronic
Anisha Paul, Buddhadev Pradhan
Summary: This paper presents a novel design of a power and energy-efficient carbon nanotube field-effect transistor (CNTFET)-based quaternary magnitude comparator for single and double digits. The study also proposes an improved circuit for a ternary single-digit comparator and a new design for a double-digit ternary comparator. By utilizing pass transistor logic and transmission gates, the designs achieve higher power and energy efficiency with a reduced number of CNTFETs compared to existing designs. Additionally, a generalized circuit for a magnitude comparator of multiple digits is proposed. The proposed circuits are simulated and analyzed for average power, propagation delays, and power-delay-product (PDP) using the 32 nm CNTFET model provided by Stanford University. The impact of process parameter variations is also investigated through Monte Carlo simulation.
CIRCUITS SYSTEMS AND SIGNAL PROCESSING
(2023)
Article
Engineering, Electrical & Electronic
Jongho Yoon, Seunghan Baek, Sunmean Kim, Seokhyeong Kang
Summary: To improve the performance of existing ternary multipliers, ternary Wallace tree multipliers that reduce the number of transistors by using 4-input ternary adders are proposed. A ternary carry-select adder is also proposed to reduce the carry propagation delay, used as a carry-chain adder of the Wallace tree. The proposed multipliers are designed with a custom ternary standard cell library synthesized by multi-threshold complementary metal-oxide-semiconductor (CMOS) with a 28 nm process. Power and delay are verified via HSPICE simulation. The proposed 36 x 36 ternary multiplier shows 79.3% power-delay product improvement over the previous ternary multiplier. The proposed 40 x 40 ternary multiplier shows a power-delay product comparable with that of the 64 x 64 binary multiplier synthesized using Synopsys Design Compiler.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
(2023)
Article
Computer Science, Information Systems
Furqan Zahoor, Fawnizu Azmadi Hussin, Farooq Ahmad Khanday, Mohamad Radzi Ahmad, Illani Mohd Nawi, Chia Yee Ooi, Fakhrul Zaman Rokhani
Summary: The latest multiple valued logic circuits have shown potential for higher storage density compared to binary circuits, attracting attention for digital system designs. Carbon nanotube field effect transistors (CNTFETs) and resistive random access memory (RRAM) are considered suitable options for MVL circuit designs, with proposed designs demonstrating advantages in terms of reduced transistor count, decreased cell area, and lower power consumption. Additionally, the participation of RRAM provides non-volatility advantages.
Article
Quantum Science & Technology
Mohammad-Ali Asadi, Mohammad Mosleh, Majid Haghparast
Summary: This study proposed a new approach to design ternary reversible multipliers that efficiently reduce the number of operations and chip occupied area, overcome energy loss, and achieve high flexibility and speed. By ignoring the most significant digit in the partial products, the computational load was successfully reduced. Furthermore, the efficiency of partial product summation was improved by designing a new reversible ternary full-adder.
QUANTUM INFORMATION PROCESSING
(2021)