Journal
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Volume 36, Issue 8, Pages 1353-1366Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCAD.2016.2618866
Keywords
Memristor; neural network hardware; synapse
Categories
Funding
- DARPA [D13AP00042]
- NSF [1311747]
- AFRL [FA8750-15-2-0048]
- HP Labs
- Direct For Computer & Info Scie & Enginr
- Division of Computing and Communication Foundations [1744077] Funding Source: National Science Foundation
- Directorate For Engineering
- Div Of Electrical, Commun & Cyber Sys [1311747] Funding Source: National Science Foundation
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Recent advances in memristor technology lead to the feasibility of large-scale neuromorphic systems by lever-aging the similarity between memristor devices and synapses. For instance, memristor cross-point arrays can realize dense synapse network among hundreds of neuron circuits, which is not affordable for traditional implementations. However, little progress was made in synapse designs that support both static and dynamic synaptic properties. In addition, many neuron circuits require signals in specific pulse shape, limiting the scale of system implementation. Last but not least, a bottom-up study starting from realistic memristor devices is still missing in the current research of memristor-based neuromorphic systems. Here, we propose a memristor-based dynamic (MD) synapse design with experiment-calibrated memristor models. The structure obtains both static and dynamic synaptic properties by using one memristor for weight storage and the other as a selector. We overcame the device nonlinearities and demonstrated spike-timing-based recall, weight tunability, and spike-timing-based learning functions on MD synapse. Furthermore, a temporal pattern learning application was investigated to evaluate the use of MD synapses in spiking neural networks, under both spike-timing-dependent plasticity and remote supervised method learning rules.
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