A Hardware-Efficient Scalable Spike Sorting Neural Signal Processor Module for Implantable High-Channel-Count Brain Machine Interfaces

Published 2017 View Full Article

Authors

Keywords

Journal

IEEE Transactions on Biomedical Circuits and Systems

Volume 11, Issue 4, Pages 743-754

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Online

2017-05-25

DOI

10.1109/tbcas.2017.2679032

Ask authors/readers for more resources

Publish scientific posters with Peeref

Peeref publishes scientific posters from all research disciplines. Our Diamond Open Access policy means free access to content and no publication fees for authors.

Learn More

Ask a Question. Answer a Question.

Quickly pose questions to the entire community. Debate answers and get clarity on the most important issues facing researchers.

Get Started

IEEE Transactions on Biomedical Circuits and Systems

Ask authors/readers for more resources

Protocol

Reagent

Reprint

Publish scientific posters with Peeref

Ask a Question. Answer a Question.