Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 52, Issue 8, Pages 2141-2153Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2017.2688364
Keywords
Analog-to-digital converter (ADC); low-voltage design; quantization noise shaping; ring oscillator; sigma-delta modulator; time-domain signal processing; voltage-controlled oscillator (VCO)
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Funding
- Fund for Scientific Research Flanders (FWO-Vlaanderen), Belgium
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This paper presents the architectural concept and implementation of a mostly digital voltage-controlled oscillator-analog- to-digital converter (VCO-ADC) with third-order quantization noise shaping. The system is based on the combination of a VCO and a digital counter. It is shown how this combination can function as a continuous-time integrator to form a high-order continuous-time sigma-delta modulator (CT-SDM). The counter consists only of digital building blocks, and the VCOs are implemented using ring oscillators, which are also digital-friendly. No traditional analog blocks, such as opamps, OTAs, or comparators, are used. As a proof of concept, we have implemented a third-order VCO-based CT-SDM for a 10-MHz bandwidth in the low-power version of a 65-nm CMOS technology. This prototype shows a measured performance of 71/66.2/62.5-dB DR/SNR/SNDR at a 10-MHz bandwidth while consuming 1.8 mW from a 1.0-V analog and 1.9 mW from a 1.2-V digital supply. With digital calibration, the nonlinearity could be pushed below the noise level, leading to an improved peak SNDR of 66 dB.
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