Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 52, Issue 10, Pages 2576-2588Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2017.2728784
Keywords
Reference buffer; reference error calibration; successive approximation register (SAR) analog-to-digital converter (ADC); threshold reconfigurable comparator
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Funding
- Macao Science and Technology Development Fund [053/2014/A1]
- University of Macau [MYRG2015-00086-AMS]
- National Natural Science Foundation of China [F040202]
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This paper presents a reference error calibration scheme for successive approximation register (SAR) analog-to-digital converters (ADCs) verified with two prototypes. Such a reference error often occurs in high-speed SAR ADCs due to the signal dependent fast switching transient, and leads to a large differential nonlinearity and missing codes, eventually degrading conversion accuracy. The calibration concept aims to differentiate the error outputs and correct them by simply performing a subtraction in the digital domain. It runs in the background with a little hardware overhead, and does not depend on the type of the input signal or reduce the dynamic range. Two prototypes were measured which are made up of different reference generation circuits. Design #1 has the reference voltage from off-chip and a 3-pF decoupling capacitor on-chip, while design #2 includes an on-chip reference buffer. Both designs were fabricated in 65-nm CMOS and achieve at least 9-dB improvement on signal-to-(Noise + Distortion) ratio (SNDR) after calibration. The total core area is around 0.012 mm(2) for both chips and the Nyquist SNDR of designs #1 and #2 is 59.03 and 57.93 dB, respectively.
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