4.7 Review

Integrated Photonic Tensor Processing Unit for a Matrix Multiply: A Review

Journal

JOURNAL OF LIGHTWAVE TECHNOLOGY
Volume 41, Issue 12, Pages 3704-3716

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JLT.2023.3269957

Keywords

Matrix-vector multiplication; photonics; PICs; silicon photonics; tensor core

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The explosion of artificial intelligence and machine-learning algorithms, along with the exponential growth of exchanged data, has led to a search for new application-specific hardware accelerators. Photonics, with its almost infinite bandwidth capacity and limited energy consumption, is in the spotlight for this global data explosion. This review discusses the advantages of photonics over electronics for hardware accelerators, compares major architectures implemented on Photonics Integrated Circuits (PIC) for linear and nonlinear parts of Neural Networks, and highlights the driving forces and limits of the next generation of photonic accelerators.
The explosion of artificial intelligence and machine-learning algorithms, connected to the exponential growth of the exchanged data, is driving a search for novel application-specific hardware accelerators. Among the many, the photonics field appears to be in the perfect spotlight for this global data explosion, thanks to its almost infinite bandwidth capacity associated with limited energy consumption. In this review, we will overview the major advantages that photonics has over electronics for hardware accelerators, followed by a comparison between the major architectures implemented on Photonics Integrated Circuits (PIC) for both the linear and nonlinear parts of Neural Networks. By the end, we will highlight the main driving forces for the next generation of photonic accelerators, as well as the main limits that must be overcome.

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