Analysis of network-on-chip topologies for cost-efficient chip multiprocessors

Authors

Keywords

Interconnection networks, Chip multiprocessor, Topology, Mesh, Torus, Ring

Journal

Volume 42, Issue -, Pages 24-36

Publisher

Elsevier BV

Online

2016-02-01

DOI

10.1016/j.micpro.2016.01.005

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