An area efficient vedic multiplier for FFT Processor implementation using 4-2 compressor adder

Design and Analysis of Efficient Vedic Multiplier for Fast Computing Applications

(2023) Aishita Verma et al.   International Journal of Computing and Digital Systems

Efficient Cached 64 Point FFT Processor Using Floating Point Arithmetic for OFDM Application

(2022) Challa Padma et al.   Instrumentation Mesure Metrologie

Low‐power fast Fourier transform hardware architecture combining a split‐radix butterfly and efficient adder compressors

(2021) Guilherme Ferreira et al.   IET Computers and Digital Techniques

High-Speed Hybrid Multiplier Design Using a Hybrid Adder with FPGA Implementation

(2021) V. Thamizharasan et al.   IETE JOURNAL OF RESEARCH

Revisiting the ECM-KEEM protocol with Vedic multiplier for enhanced speed on FPGA platforms

(2021) C. T. Poomagal et al.   Journal of Ambient Intelligence and Humanized Computing

Area and power-efficient variable-length fast Fourier transform for MR-OFDM physical layer of IEEE 802.15.4-g

(2020) Ganjikunta Ganesh Kumar et al.   IET Computers and Digital Techniques

A modular Vedic multiplier architecture for model-based design and deployment on FPGA platforms

(2020) Valentina Bianchi et al.   MICROPROCESSORS AND MICROSYSTEMS

Design and performance analysis of reconfigurable modified Vedic multiplier with 3-1-1-2 compressor

(2019) K. Sivanandam et al.   MICROPROCESSORS AND MICROSYSTEMS

Towards design and automation of a scalable split-radix FFT processor for high throughput applications

(2019) Adnan Rauf et al.   MICROPROCESSORS AND MICROSYSTEMS

An Imprecise 4-2 Compressor Design Used in Image Processing Applications

(2019) Yen-Jen Chang et al.   IET Circuits Devices & Systems

Hardware Implementation of FFT/IFFT Algorithms Incorporating Efficient Computational Elements

(2019) Konguvel Elango et al.   Journal of Electrical Engineering & Technology

Approximate Multipliers Based on New Approximate Compressors

(2018) Darjn Esposito et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers

(2017) Omid Akbari et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

An area-efficient and low-power 64-point pipeline Fast Fourier Transform for OFDM applications

(2017) Ganesh Kumar Ganjikunta et al.   INTEGRATION-THE VLSI JOURNAL

Design and Analysis of Multiplier Using Approximate 15-4 Compressor

(2017) R. Marimuthu et al.   IEEE Access

A novel high-speed approach for 16 × 16 Vedic multiplication with compressor adders

(2016) Yogita Bansal et al.   COMPUTERS & ELECTRICAL ENGINEERING

Design and Analysis of Approximate Compressors for Multiplication

(2015) Amir Momeni et al.   IEEE TRANSACTIONS ON COMPUTERS

A High-Throughput Low-Complexity Radix- $2^{\textbf {4}}$ - $2^{\textbf {2}}$ - $2^{\textbf {3}}$ FFT/IFFT Processor With Parallel and Normal Input/Output Order for IEEE 802.11ad Systems

(2015) Chao Wang et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems

(2015) Jienan Chen et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Coarse Grained ADRES Based MIMO-OFDM Transceiver with New Radix- $${2}^{5}$$ 2 5 Pipeline FFT/IFFT Processor

(2014) N. Janakiraman et al.   CIRCUITS SYSTEMS AND SIGNAL PROCESSING

Design of power efficient butterflies from Radix-2 DIT FFT using adder compressors with a new XOR gate topology

(2012) Mateus Beck Fonseca et al.   ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING

A High-Speed Low-Complexity Modified ${\rm Radix}-2^{5}$ FFT Processor for High Rate WPAN Applications

(2012) Taesang Cho et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

A low-power 64-point pipeline FFT/IFFT processor for OFDM applications

(2011) Chu Yu et al.   IEEE TRANSACTIONS ON CONSUMER ELECTRONICS

Radix $r^{k} $ FFTs: Matricial Representation and SDC/SDF Pipeline Implementation

(2009) A. Cortes et al.   IEEE TRANSACTIONS ON SIGNAL PROCESSING