Asynchronous Single Flux Quantum Logic Gates Using Self-Clocking

Rapid Single-Flux-Quantum Logic Circuits Using Clockless Gates

(2021) Takahiro Kawaguchi et al.   IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY

64-GHz Datapath Demonstration for Bit-Parallel SFQ Microprocessors Based on a Gate-Level-Pipeline Structure

(2021) Ryota Kashima et al.   IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY

Fabrication Process for Superconducting Digital Circuits

(2021) Mutsuo HIDAKA et al.   IEICE TRANSACTIONS ON ELECTRONICS

32-Bit ALU with Clockless Gates for RSFQ Bit-Parallel Processor

(2021) Takahiro KAWAGUCHI et al.   IEICE TRANSACTIONS ON ELECTRONICS

Asynchronous Dynamic Single-Flux Quantum Majority Gates

(2020) Gleb Krylov et al.   IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY

Clockless Dynamic SFQ and Gate With High Input Skew Tolerance

(2019) Sergey V. Rylov   IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY

Demonstration of Picosecond Time Resolution in Double-Oscillator Time-to-Digital Converter Using Single-Flux-Quantum Circuits

(2019) Yuma Tomitsuka et al.   IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY

Globally Asynchronous, Locally Synchronous Clocking and Shared Interconnect for Large-Scale SFQ Systems

(2019) Gleb Krylov et al.   IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY

PBMap: A Path Balancing Technology Mapping Algorithm for Single Flux Quantum Logic Circuits

(2018) Ghasem Pasandi et al.   IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY

Adiabatic quantum-flux-parametron cell library designed using a 10 kA cm−2niobium fabrication process

(2017) Naoki Takeuchi et al.   SUPERCONDUCTOR SCIENCE & TECHNOLOGY

Improvement of Operating Margin of SFQ Circuits by Controlling Dependence of Signal Propagation Time on Bias Voltage

(2012) M. Otsubo et al.   IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY

8-Bit Asynchronous Wave-Pipelined RSFQ Arithmetic-Logic Unit

(2011) T. Filippov et al.   IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY

Comparisons of Synchronous-Clocking SFQ Adders

(2010) Naofumi TAKAGI et al.   IEICE TRANSACTIONS ON ELECTRONICS

Design of fast digit-serial adders using SFQ logic circuits

(2009) Heejoung Park et al.   IEICE Electronics Express