Energy-Efficient Single-Ended Read/Write 10T Near-Threshold SRAM

Modern system-on-chip-based applications require low-power/energy SRAMs for long-term operation. To deal with this issue, near-threshold SRAM design is an effective approach. In this regard, this paper presents an energy-efficient single-ended 10T (SE10T) near-threshold SRAM. The proposed SE10T improves read stability and writability with the help of a built-in read-assist scheme and a power-gating technique, respec-tively, and reduces power/energy consumption by using single-ended read/write operation and stacking of transistors in the cell core. Simulation results in 32-nm CMOS technology at a 0.6 V show that the proposed design improves read stabil-ity/writability by 3.03x/1.35x, reduces leakage power by 46.09%, and offers improvements of 86.09%/88.81% and 73.82%/62.72% in read/write power and read/write energy, respectively, in com-parison with the conventional 6T SRAM. The minimum operation voltage of the proposed design is the lowest (Vmin = 590 mV), which is reduced by 41% compared to the conventional 6T. However, read/write delay in the proposed design is increased by 2.48x/5.40x due to being single-ended, and the layout area of the proposed design is 1.893 mu m2, which is 1.82x larger than that of the conventional 6T.

Automated summary

This paper proposes an energy-efficient single-ended 10T near-threshold SRAM design, which improves read stability and writability with a built-in read-assist scheme and power-gating technique, reduces power/energy consumption through single-ended read/write operation and transistor stacking. Compared with the conventional 6T SRAM, simulation results in 32-nm CMOS technology at 0.6V show that the proposed design improves read stability/writability by 3.03x/1.35x, reduces leakage power by 46.09%, and offers significant improvements in read/write power and energy. However, the proposed design has higher read/write delay and larger layout area than the conventional 6T.