A Highly Stable Low-Energy 10T SRAM for Near-Threshold Operation

This paper aims to explore the design of a novel highly stable low-energy 10T (SLE10T) SRAM cell for near-threshold operation. The latch core of the proposed design consists of a cross-coupled structure of a tri-state inverter and a standard inverter. The tri-state inverter is switched to the high-impedance mode during a write operation to temporarily float the data node, improving writability. In addition, read stability is equivalent to hold stability due to considering a separate path for read current flow, as well as a built-in read-assist scheme to force the '0' storing node to ground. Leakage and dynamic power consumptions in the designed cell are reduced with the help of single-bitline structure and stacking of transistors. The simulation results in a 7-nm FinFET at a 0.5 V show that the SLE10T improves read stability by at least 1.31 times compared to read-disturbance SRAMs and offers the second-highest writability, improvement of at least 1.10x . Leakage power dissipation is reduced in the SLE10T by at least 1.10x. Moreover, it improves read/write energy by at least 1.01 x /1.03x. However, the area of the SLE10T bitcell is 0.02 mu m(2), which is 1.657 x /1.318 x larger than the conventional 6T/8T bitcell.

Automated summary

This paper presents a novel design for a highly stable and low-energy SRAM cell. The design includes a cross-coupled structure of a tri-state inverter and a standard inverter, improving writability by floating the data node during write operations. Read stability is enhanced by considering a separate path for read current flow and employing a read-assist scheme. Leakage and dynamic power consumption are reduced through the use of a single-bitline structure and transistor stacking. Simulation results demonstrate improved read stability and writability compared to other SRAM cells, as well as reduced power consumption. The only drawback is the larger area of the proposed design.