Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques

This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications.

Automated summary

This paper presents an overview of low-power successive approximation register analog-to-digital converters, covering operation principles, error analysis, and practical design issues. It also provides a comprehensive survey of low-power design techniques for each circuit block in the SAR ADC. The goal is to assist SAR ADC designers in improving energy efficiency for low-to-medium speed applications.