A Low-Noise Low-Power Chopper Instrumentation Amplifier With Robust Technique for Mitigating Chopping Ripples

Capacitively coupled chopper instrumentation amplifier (CCIA) is a classical topology for designing low-noise, low-power instrumentation amplifiers (IAs). However, CCIA has two significant limitations: chopping ripple and limited input impedance. Especially for ultra-low-noise applications, the chopping ripple of CCIA can easily saturate the amplifier. Hence, ripple reduction (RR) is required in the CCIA design. This article presents a CCIA with a newly proposed chopping RR technique, dynamic offset zeroing (DOZ). By introducing an ultra-low duty cycle zeroing phase in the normal chopping operation, the proposed DOZ technique can suppress the chopping ripple with a measured state-of-the-art reduction ratio of 61 dB while introducing negligible noise, power, and circuit overhead. In addition, a highly linear three-terminal varactor is proposed in a positive feedback loop (PFL) to boost the limited input impedance of the CCIA to be above 1 G omega. The presented CCIA is implemented in a 180-nm CMOS technology and achieves a 13-nV/root Hz input-referred noise density and a noise efficiency factor (NEF) of 1.3 while consuming 4.5-mu W power.

Automated summary

Capacitively coupled chopper instrumentation amplifier (CCIA) is a classical topology for designing low-noise, low-power instrumentation amplifiers. This article introduces a newly proposed chopping ripple reduction technique and a method to improve the input impedance of CCIA. Experimental results demonstrate the effectiveness of these approaches.