Design and Analysis of Linear Phase Finite Impulse Response Filter Using Water Strider Optimization Algorithm in FPGA

In this manuscript, an optimal linear phase finite impulse response (FIR) filter is designed using water strider optimization algorithm and implemented in the field programmable gate array (FPGA). The initiative behind the linear phase FIR filter design is to estimate the coefficients of optimum filter. Here, the water strider optimization algorithm is proposed to evaluate the optimal filter coefficients (LPFIR-WSOA filter). The proposed LPFIR-WSOA filter attains 32.57, 19.09, 28.07, 27.42, 24.91 and 12.72% lower maximum pass ripple compared with the existing linear phase FIR filter. Finally, the proposed LPFIR-WSOA filter is implemented in FPGA for real-time application with the target families of Virtex 6 and Virtex 7. For target FPGA families Virtex 6, the FPGA-LPFIR-WSOA filter provides 16.7910, 15.074 and 18.065% lower maximum clock frequency (MHz); 62.3837, 41.9554 and 56.078% lower delay; and 23.7172, 20.324 and 26.417% lower memory usage compared with the existing LPFIR filters like global best steered quantum-inspired cuckoo search algorithm in FPGA (FPGA-FIR-GQICSA), modified artificial bee colony optimization-based FIR filter design in FPGA (FPGA-FIR-MABCO) and hybrid artificial bee colony algorithm-based FIR filter design in FPGA (FPGA-FIR-HABCA), respectively.

Automated summary

This manuscript presents the design and implementation of an optimal linear phase finite impulse response (FIR) filter using the water strider optimization algorithm in the field programmable gate array (FPGA). The proposed filter achieves lower maximum pass ripple compared to existing linear phase FIR filters. Additionally, the FPGA implementation of the proposed filter offers lower clock frequency, delay, and memory usage compared to other FIR filters.