4.3 Article

FELIX: A Ferroelectric FET Based Low Power Mixed-Signal In-Memory Architecture for DNN Acceleration

Journal

Publisher

ASSOC COMPUTING MACHINERY
DOI: 10.1145/3529760

Keywords

FeFET crossbar array; in-memory computation; convolution neural networks; mixed-signal processing; bit-decomposition; current-mode ADC

Funding

  1. ECSEL Joint Undertaking project TEMPO
  2. European Union [826655]
  3. Carl Zeiss Foundation under the grant Sustainable Embedded AI

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In this article, a new mixed-signal in-memory architecture based on the bit-decomposition of the multiply and accumulate (MAC) operations is proposed to improve the throughput and energy efficiency of deep neural network (DNN) computing systems. Compared to previous work, this architecture provides higher parallelism, lower power consumption, and higher utilization efficiency, without the need for any digital-to-analog converters (DACs). Simulation results demonstrate superior performance in terms of area and power compared to state-of-the-art techniques.
Today, a large number of applications depend on deep neural networks (DNN) to process data and perform complicated tasks at restricted power and latency specifications. Therefore, processing-in-memory (PIM) platforms are actively explored as a promising approach to improve the throughput and the energy efficiency of DNN computing systems. Several PIM architectures adopt resistive non-volatile memories as their main unit to build crossbar-based accelerators for DNN inference. However, these structures suffer from several drawbacks such as reliability, low accuracy, large ADCs/DACs power consumption and area, high write energy, and so on. In this article, we present a new mixed-signal in-memory architecture based on the bit-decomposition of the multiply and accumulate (MAC) operations. Our in-memory inference architecture uses a single FeFET as a non-volatile memory cell. Compared to the prior work, this system architecture provides a high level of parallelism while using only 3-bit ADCs. Also, it eliminates the need for any DAC. In addition, we provide flexibility and a very high utilization efficiency even for varying tasks and loads. Simulations demonstrate that we outperform state-of-the-art efficiencies with 36.5 TOPS/W and can pack 2.05 TOPS with 8-bit activation and 4-bit weight precision in an area of 4.9 mm(2) using 22 nm FDSOI technology. Employing binary operation, we obtain 1169 TOPS/W and over 261 TOPS/W/mm(2) on system level.

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